Advanced Packaging (CoWoS / SoIC)

Active
TSMC
TSMC

Overview

TSMC's 2.5D and 3D packaging technologies that integrate GPU dies with stacks of high-bandwidth memory on silicon interposers — the technology every leading AI accelerator depends on, and for two years the binding constraint on global AI chip supply. Capacity is being expanded roughly fourfold from late-2024 levels, including the new AP7 plant in Chiayi and two planned Arizona packaging facilities.

Aggressive expansion toward ~130k CoWoS wafers/month by end of 2026, up from ~35k in late 2024; 10–20% of the 2026 capital budget

Key Specs

CoWoS capacity target

~130k wafers/month by late 2026 (~4x late-2024)

Share of 2026 capex

10–20% of $60–64B